Programmable logic devices (PLDs) perform logic functions quickly on a multiplicity of input signals. As shown in FIG. 1 to which reference is now made, an array of PLDs, labeled 12, receives input signals via input/output blocks 8. The results of the logic functions are known as "product terms" and are output from the PLD array 12 to one or more blocks 8, each of which comprises a macrocell 14 and an input/output unit 16.
Each macrocell 14 comprises an OR gate 20, a XOR gate 21, a flip-flop 22 and a multiplexer 24. The OR gate 20 performs OR operations on at least two "OR-PT" type product terms and the XOR gate 21 selectively passes or inverts the output of OR gate 20. The result is provided to the data (D) input of the flip-flop 22. Other product term signals, such as the CLOCK-PT, PRESET-PT and CLEAR-PT product terms, control the operation of flip-flop 22, where the CLOCK-PT is a clock signal, the PRESET-PT activates flip-flop 22 (providing a "1" signal on output) and CLEAR-PT deactivates flip-flop 22 (providing a "0" signal on output). The output of flip-flop 22 is a "registered" signal and can be selected by multiplexer 24 for the output signal of macrocell 14. Alternatively, multiplexer 24 can select the data input to flip-flop 22, otherwise known as a "combinatorial" signal. The registered signal might be needed to determine other product term signals and, therefore, is provided to PLD array 12 as a "register feedback" signal.
Typically, the output signal of PLD array 12 is utilized to control an external unit, such as opening or closing a switch. The output signal is therefore provided to input/output unit 16 comprised of a configurable buffer 26 and an external pin 28 to which the external unit is connected. Buffer 26 is configured by an output enable (OE) product term signal which indicates if buffer 26 is to function as an output buffer, for controlling an output signal, or as an input buffer through which to receive signals. In the latter case, the input signal is provided directly to the PLD array 12, in effect bypassing the macrocell 14.
In the programmable system devices (PSDs) of Waferscale Integration Inc. of Fremont, Calif., USA, the common assignees of the present invention, and in other devices, such as the MACH devices manufactured by American Microsystems Devices also of California or the MAX devices of Altera also of California. PLD array 12 functions in part as a peripheral device of a microcontroller 10 and, as a result, microcontroller 10 has to read from and write to the macrocells 14. The read operation should occur without affecting the output signal of the macrocell 14. For example, if PLD array 12 implements a counter, microcontroller 10 might want either to load the counter with a new value or read the current value of the counter.
However, every microcontroller 10 reads data by placing the address to read from on an address bus 30 and waiting for the peripheral to place the data 32 to be read on a data bus. Similarly, the address to be written to is placed on address bus 30 and the data to be written is placed on data bus 32. Furthermore, the signal to read or write is provided separately, as indicated by signals 34 and 36, respectively.
The address and data include N and M bits, respectively, where N is typically sixteen and M is typically eight. Thus, busses 30 and 32 are connected to N and M input/output blocks, shown as a single block 40 and 42, respectively. The input/output block for the read and write signals is labeled 44. For the address bits and the read and write signals, all of which are input signals, the corresponding buffers 26 are configured as input buffers and the address bits are provided along the input lines to the PLD array 12. PLD array 12 decodes the address bits to determine which macrocell 14 to access.
The macrocell 14 which is accessed must either provide the data stored in its flip-flop 22 out to PLD array 12 or receive data therefrom. In response, the PLD array 12 either provides the data to or receives data from a macrocell 14 connected to data bus 32.
For a write operation, the buffers 26 of the macrocell connected to data bus 32 are configured as input buffers and the data bits are passed through PLD array 12 to the accessed macrocell 14. To actually write a data bit into the flip-flop 22 of the accessed macrocell 14, PLD array 12 either sets the OR-PT signal which is clocked into flip-flop 22 by the CLOCK-PT signal or selects one or other of the PRESET-PT and CLEAR-PT signals, depending on the value (1 or 0) to be written in.
For data to be read from an accessed macrocell 14, the accessed macrocell 14 first provides the data to the PLD array 12 through the register feedback signal. The PLD array 12 then provides the data bits as the combinatorial output of the macrocells 14 connected to the data bus 32. As will be appreciated, for the data bits, the output enable (OE-PT) signal of the macrocells connected to the data bus and of the accessed macrocells changes depending on whether the read (i.e. output) or write (i.e. input) signal has been asserted.
It will be appreciated that accessing data with a PLD array requires three groups of macrocells, one group connected to the address bus, a second group of one being the macrocell being accessed and a third group connected to the data bus. Furthermore, the PLD array 12 has to route data through it twice, once from the macrocells connected to the address bus to the accessed macrocell and once from the accessed macrocell to the macrocells connected to the data bus.
It will further be appreciated that routing data and address information through PLD array 12 additionally requires that the bus signals follow standard timing. FIG. 2, to which reference is now briefly made, illustrates the timing of a single read/write cycle. The microcontroller begins by driving the address bus with an address 50, as indicated in graph A. The address is decoded, usually by an external unit (not shown) and a select signal is generated to the selected peripheral, such as PLD 12. The peripheral then waits for the next phase of the bus cycle when microcontroller asserts either the read or the write signal, as indicated in graph B.
In a read cycle, the peripheral responds by driving data bus with the required information, labeled 52, and microcontroller latches the data at a rising edge 54 of the read signal. In a write cycle, microcontroller provides data 52 and the peripheral latches data 52 at the rising edge 54 of the write pulse.
It will be appreciated that race conditions can occur between the data and the read/write signals due to violations of the bus setup and hold timing which occur since PLD 12 has delays therein. Furthermore, since the PLD 12 powers up every time it receives a signal, the fact that the address and data busses are connected to the PLD 12 will cause every change in the bus to trigger a power up/power down cycle of PLD 12. This continual cycling adds to consumes power.
Still further, routing the address and data bus data through the macrocells utilizes the critical PRESET, CLEAR, CLOCK and OR product terms, making it hard to implement the remaining logic functions which the PLD array must perform, not to mention the time required to develop the logic functions which respond to the address and data bus signals.